A frequency synthesizer, such as a phase-locked loop (PLL) can be used to provide a clock signal of a desired frequency. The PLL generates the clock signal based on a reference dock signal of a reference oscillator. An integer-N PLL is capable of generating a dock signal having a frequency that is an integer multiple of the reference frequency. A fractional-N PLL is capable of generating a clock signal having a frequency that is a non-integer multiple of the reference frequency. A fractional-N PLL is more flexible than an integer-N PLL due to its higher frequency resolution. Compared with an integer-N PLL, however, a fractional-N PLL can exhibit increased phase noise (jitter) due to generation of fractional boundary spurs (“fractional jitter”). To reduce fractional jitter, designers typically reduce the bandwidth of the fractional-N PLL. A greater ratio of the reference clock frequency to the PLL bandwidth leads to better jitter rejection. Such a reduction in PLL bandwidth, however, results in longer lock times and can cause excessive voltage controlled oscillator (VCO) phase noise to appear at the PLL output leading to higher random jitter. It is therefore desirable to reduce fractional jitter without the need to reduce PLL bandwidth.